The present invention relates generally to the synchronization of graphics processing in a computer system with multiple graphics processing units (GPUs), and, more particularly, to the timing of image rendering and flipping.
Modern computer systems often employ multiple graphics processing units (GPUs) to render images simultaneously, and these images are stored in multiple buffers. A particular GPU, often called master GPU, connects to a display driver. All the images are displayed from one or more buffers associated with the master GPU through a flip operation by a graphics driver. A flip is to turn a previously front buffer into a back one, and a previously back one into a front one. The so called ‘front buffer’ is a buffer currently supplying an image to the display driver, and the back buffer is one that is ready to receive an image either from rendering or from bit-block-transferring.
Bit-block-transfer (BLT) is to combine two image (e.g., bitmap) patterns from two buffers into one. Since only one master GPU do the flip, all other GPU are slaves. The images rendered by slave GPUs are eventually bit-block-transferred from their own buffers to the master buffers associated with the master GPU. The graphics driver also manages BLT timing and storage locations in the source as well as target buffers for the rendered and subsequently transferred images. The graphics driver can flip among any number of buffers, yet traditional double buffers remains to be the simplest for the driver to handle and hence most desirable. But in any case, the driver has to synchronize the flip, rendering and BLT, and for that, the traditional way of continuously checking the status of each and every component, i.e., GPUs, buffers, etc., is less efficient.
It is therefore desirable for a computer system to have a unified, and efficient way to synchronize these events.